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  DG406B/407b vishay siliconix new product document number: 72552 s-32513?rev. a, 29-dec-03 www.vishay.com 1 16-ch/dual 8-ch high-performance cmos analog multiplexers features benefits applications  low on-resistance?r ds(on) : 45  low charge injection?q: 11 pc  fast transition time?t trans: 115 ns  low power: 0.2 mw  single supply capability  higher accuracy  reduced glitching  improved data throughput  reduced power consumption  increased ruggedness  wide supply ranges:  5 v to  20 v  data acquisition systems  audio signal routing  medical instrumentation  ate systems  battery powered systems  high-rel systems  single supply systems description the DG406B is a 16-channel single-ended analog multiplexer designed to connect one of sixteen inputs to a common output as determined by a 4-bit binary address. the dg407b selects one of eight differential inputs to a common differential output. break-before-make switching acti on protects against momentary shorting of inputs. an on channel conducts current equally well in both directions. in the off state each channel blocks voltages up to the power supply rails. an enable (en) function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. all control inputs, address (a x ) and enable (en) are ttl compatible over the full specif ied operating temperature range. applications for the DG406B/407b include high speed data acquisition, audio signal switching and routing, ate systems, and avionics. high performance and low power dissipation make them ideal for battery operated and remote instrumentation applications. designed in the 44-v silicon-gate cmos process, the absolute maximum voltage rating is extended to 44 volts, allowing operation with  20-v supplies. additionally si ngle (12-v) supply operation is allowed. an epitaxial layer prevents latchup. functional block diagram and pin configuration dg407b v+ s 3b s 2b s 1b nc nc d a s 2a s 1a gnd a 1 a 2 d b dual-in-line and soic wide-body a 0 en v- nc s 8a s 8b s 7a s 7b s 6a s 6b s 5a s 5b s 4a s 4b s 3a 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 top view 920 10 19 11 12 18 17 13 16 14 15 v+ s 11 s 10 s 9 nc a 3 d s 2 s 1 gnd a 1 a 2 nc dual-in-line and soic wide-body a 0 en v- nc s 8 s 16 s 7 s 15 s 6 s 14 s 5 s 13 s 4 s 12 s 3 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 top view 920 10 19 11 12 18 17 13 16 14 15 DG406B decoders/drivers decoders/drivers
DG406B/407b vishay siliconix new product www.vishay.com 2 document number: 72552 s-32513?rev. a, 29-dec-03 functional block diagram and pin configuration decoders/drivers plcc and lcc 7 8 9 5 20 19 21 22 23 24 25 1 2 3 4 10 11 12 13 14 15 16 17 18 26 27 28 top view 6 s 7b s 5a s 4b s 4a s 7a s 3b s 6b s 6a s 3a s 5b s 2b s 2a s 1b s 1a plcc and lcc top view gnd nc nc d nc v+ d v- en s 2 1 0 s a a a 8b 8a b a dg407b s 13 s 15 s 5 s 12 s 4 s 7 s 11 s 14 s 6 s 3 s 10 s 2 s 9 s 1 s gnd nc nc nc 3 v+ 2 d 1 v- 0 s en DG406B a a a a 16 8 decoders/drivers 7 8 9 5 20 19 21 22 23 24 25 1 2 3 4 10 11 12 13 14 15 16 17 18 26 27 28 6 truth table DG406B a 3 a 2 a 1 a 0 en on switch x x x x 0 none 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 truth table dg407b a 2 a 1 a 0 en on switch pair x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 logic ?0? = v al  0.8 v logic ? 1 ?= v ah  2.4 v l og i c ?1? = v ah  2 . 4 v x = don?t care ordering information DG406B temp range package part number 28-pin plastic dip DG406Bdj - 40 to 85  c 28-pin plcc DG406Bdn 28-pin widebody soic DG406Bdw 55 to 125  c 28-pin cerdip DG406Bak/883 - 55 to 125  c lcc-28 DG406Baz/883 ordering information dg407b temp range package part number 28-pin plastic dip dg407bdj - 40 to 85  c 28-pin plcc dg407bdn 28-pin widebody soic dg407bdw 55 to 125  c 28-pin cerdip dg407bak/883 - 55 to 125  c lcc-28 dg407baz/883
DG406B/407b vishay siliconix new product document number: 72552 s-32513?rev. a, 29-dec-03 www.vishay.com 3 absolute maximum ratings voltages referenced to v - v+ 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a , v s , v d (v -) -2 v to (v+) +2 v or . . . . . . . . . . . . . . . . . . . . . . . . 20 ma, whichever occurs first current (any t erminal,) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature -65 to 150  c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (package) b 28-pin plastic dip c 625 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-pin cerdip d 1.2 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-pin plastic plcc c 450 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lcc-28 e 1.35 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-pin widebody soic f 450 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x or in x exceeding v+ or v - will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 8.3 mw/  c above 75  c d. derate 16 mw/  c above 75  c e. derate 18 mw/  c above 75  c f. derate 6 mw/  c above 75  c specifications test conditions unless otherwise specified a suffix - 55 to 125  c d suffix - 40 to 85  c parameter symbol v+ = 15 v, v - = -15 v v al = 0.8 v, v ah = 2.4 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full -15 15 -15 15 v drain-source on-resistance r ds(on) v d =  10 v, i s = - 10 ma sequence each switch on room full 45 60 87 60 74 r ds(on) matching between channels g r ds(on) v d =  10 v room 5 % source off leakage current i s(off) v 0 v room full -0.5 -50 0.5 50 -0.5 -5 0.5 5 drain off i d( ff) v en = 0 v v d =  10 v v s =  10 v DG406B room full -1 -200 1 200 -1 -40 1 40 drain off leakage current i d(off) v s =  10 v dg407b room full -1 -100 1 100 -1 -20 1 20 na drain on i d( ) v s = v d =  10 v sequence each DG406B room full -1 -200 1 200 -1 -40 1 40 drain on leakage current i d(on) sequence each switch on dg407b room full -1 -100 1 100 -1 -20 1 20 digital control logic high input voltage v inh full 2.4 2.4 v logic low input voltage v inl full 0.8 0.8 v logic high input current i ah v a = 2.4 v, 15 v full -1 1 -1 1 a logic low input current i al v en = 0 v, 2.4 v, v a = 0 v full -1 1 -1 1 a logic input capacitance c in f = 1 mhz room 6 pf dynamic characteristics transition time t trans see figure 2 room full 115 148 170 148 161 break-before-make interval t open see figure 4 room full 39 10 29 10 21 ns enable turn-on time t on(en) see figure 3 room full 75 107 134 107 123 ns enable turn-off time t off(en) see figure 3 room full 50 88 98 88 94 charge injection q c l = 1 nf, v s = 0 v, r s = 0 room 11 pc off isolation h oirr v en = 0 v, r l = 50 f = 1 mhz room -86 db source off capacitance c s(off) v en = 0 v, v s = 0 v, f = 1 mhz room 6 drain off capacitance c d( ff) room 108 drain off capacitance c d(off) v en = 0 v, v d = 0 v dg407b room 54 pf drain on capacitance c d( ) v en = 0 v , v d = 0 v f = 1 mhz DG406B room 114 p drain on capacitance c d(on) dg407b room 57
DG406B/407b vishay siliconix new product www.vishay.com 4 document number: 72552 s-32513?rev. a, 29-dec-03 specifications d suffix - 40 to 85  c a suffix - 55 to 125  c test conditions unless otherwise specified parameter unit max d min d max d min d typ c temp b v+ = 15 v, v - = -15 v v al = 0.8 v, v ah = 2.4 v f symbol power supplies positive supply current i+ v en = v a = 0 or 5 v room full 23 30 75 30 75 negative supply current i- v en = v a = 0 or 5 v room full -0.02 -1 -10 -1 -10 a positive supply current i+ v en = 2 4 v v a = 0 v room full 28 500 900 500 700 a negative supply current i- v en = 2.4 v, v a = 0 v room full -0.01 -20 -20 -20 -20 specifications for single supply test conditions unless otherwise specified a suffix - 55 to 125  c d suffix - 40 to 85  c parameter symbol v+ = 12 v, v - = 0 v v al = 0.8 v, v ah = 2.4 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full 0 12 0 12 v drain-source on-resistance r ds(on) v d = 3 v, 10 v, i s = - 1 ma room 78 100 100 r ds(on) matching between channels g r ds(on) v d = 3 v , 10 v , i s = - 1 ma sequence each switch on room 5 % source off leakage current a i s(off) v en = 0 v v 10 v 0 5 v room -0.5 0.5 -0.5 0.5 drain off i d( ff) en 0 v d = 10 v or 0.5 v v s = 0.5 v or 10 v DG406B room -1 1 -1 1 a drain off leakage current a i d(off) v s = 0 . 5 v or 10 v dg407b room -1 1 -1 1 na drain on i d( ) v s = v d =  10 v DG406B room -1 1 -1 1 drain on leakage current a i d(on) v s = v d =  10 v sequence each switch on dg407b room -1 1 -1 1 dynamic characteristics switching t ime of multiplexer t trans v s1 = 8 v, v s8 = 0 v, v in = 2.4 v room 130 163 163 enable turn-on time t on(en) v inh = 2.4 v, v inl = 0 v room 93 125 125 ns enable turn-off time t off(en) v inh = 2 . 4 v , v inl = 0 v v s1 = 5 v room 63 94 94 charge injection q c l = 1 nf, v s = 6 v, r s = 0 room 9 pc power supplies positive supply current i+ v en = 0 v or 5 v v a = 0 v or 5 v room full 13 30 75 30 75 a negative supply current i- v en = 0 v or 5 v, v a = 0 v or 5 v room full -0.01 -20 -20 -20 -20 a notes: a. guaranteed by  15-v leakage test, not production tested. b. room = 25  c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. g. r ds(on) = r ds(on) max - r ds(on) min. h. worst case isolation occurs on channel 4 due to proximity to the drain pin.
DG406B/407b vishay siliconix new product document number: 72552 s-32513?rev. a, 29-dec-03 www.vishay.com 5 typical characteristics (25  c unless noted) 5 25 45 65 85 105 125 -20 -15 -10 -5 0 5 10 15 20 on-resistance vs. v d and dual supply voltage r ds(on) - drain-source on-resistance ( ) v d - drain voltage (v) t a = 25  c  5 v  8 v  10 v  12 v  15 v  20 v 0 50 100 150 200 250 300 350 0 2 4 6 8 10 12 14 16 18 20 22 v+ = 5.0 v t a = 25  c on-resistance vs. v d and unipolar supply voltage r ds(on) - drain-source on-resistance ( ) v d - drain voltage (v) v+ = 12 v v+ = 15 v v+ = 20 v 5 15 25 35 45 55 65 75 85 -15 -10 -5 0 5 10 15 -55  c v  =  15 v on-resistance vs. v d and temperature 25  c r ds(on) - drain-source on-resistance ( ) v d - drain voltage (v) 125  c 5 25 45 65 85 105 125 145 024681012 -55  c on-resistance vs. v d and temperature 25  c r ds(on) - drain-source on-resistance ( ) v d - drain voltage (v) 125  c v+ = 12 v v - = 0 v -200 -150 -100 -50 0 50 100 150 200 -15 -10 -5 0 5 10 15 leakage vs. analog voltage v d or v s - drain or source voltage (v) i d(off) v  =  15 v t a = 25  c i d , i s (pa) i d(on) i s(off) -80 -60 -40 -20 0 20 40 60 80 100 120 140 1 1000 10000 leakage vs. current temperature (  c) 10 100 leakage (pa) i d(off) i d(on) i s(off) v+ = 10 v v+ = 22.v 85  c 85  c v  =  15 v
DG406B/407b vishay siliconix new product www.vishay.com 6 document number: 72552 s-32513?rev. a, 29-dec-03 typical characteristics (25  c unless noted) supply current vs. input switching frequency input switching frequency (hz) 10 100 1 k 10 k 100 k 1 m 10 m 1 00 p 10 n 100 n 1 m 100 m 1 10 100 supply current (na) i+ - 10 m 1 n v  =  15 v i+ 25 50 75 100 125 150 175 200 t on(en) supply voltage (v) t trans t off(en) switching time vs. bipolar supplies time (ns)  5  10  15  20 25 50 75 100 125 150 175 200 225 250 275 300 5 101520 t on(en) supply voltage (v) t trans t off(en) switching time vs. single supplies time (ns) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 5 1015202530 - switching threshold (v) v+ - supply voltage (v) switching threshold vs. supply voltage v t talk 100 k -110 1 m -30 10 -70 -50 100 m 1 g frequency (hz) -90 insertion loss, off -isolation crosstalk vs. frequency loss 10 m -10 loss, oirr, x (db) oirr x talk -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 -15 -12 -9 -6 -3 0 3 6 9 12 15 v s - analog voltage (v) charge injection vs. analog voltage q - charge injection (pc) v = 15 v v+ = 12 v c = 1 nf i- v+ = 15 v v - = -15 v r l = 50 v = 5 v
DG406B/407b vishay siliconix new product document number: 72552 s-32513?rev. a, 29-dec-03 www.vishay.com 7 typical characteristics (25  c unless noted) 25 50 75 100 125 150 175 200 -55 -35 -15 5 25 45 65 85 105 125 switching time vs. temperature temperature (  c) t on v =  15 v t off v =  15 v time (ns) t trans v =  15 v schematic diagram (typical channel) figure 1. en a 0 gnd s 1 v+ d v+ s n v- decode/ drive level shift v- v+ v ref a x
DG406B/407b vishay siliconix new product www.vishay.com 8 document number: 72552 s-32513?rev. a, 29-dec-03 test circuits figure 2. transition time logic input switch output v s8 v o t trans t r <5 ns t f <5 ns s 8 on s 1 on t trans 0 v v s1 50% 90% 90% 3 v 0 v DG406B s 1b s 8b a 2 d b a 1 * a 0 * = s 1a - s 8a , s 2b - s 7b , d a 50 300 v o  10 v  10 v +2.4 v +15 v -15 v en v+ v- gnd 35 pf s 1 s 2 - s 15 s 16 a 2 a 1 a 0 50 300 v o a 3  10 v  10 v +2.4 v +15 v -15 v en v+ v- gnd d 35 pf dg407b figure 3. enable switching time v o t r <5 ns t f <5 ns v o logic input t on(en) 90% switch output 50% t off(en) 3 v 0 v 0 v a 1 50 a 0 s 1 v o a 2 -5 v +15 v -15 v 300 en s 2 - s 16 v+ v- gnd d 35 pf a 3 v o s 1b a 2 s 1a - s 8a s 2b - s 8b a 1 d a and d b a 0 50 300 +15 v -15 v en v+ v- gnd 35 pf DG406B dg407b -5 v 90%
DG406B/407b vishay siliconix new product document number: 72552 s-32513?rev. a, 29-dec-03 www.vishay.com 9 test circuits figure 4. break-before-make interval 50% 80% logic input switch output v o v s t open t r <5 ns t f <5 ns 0 v 3 v 0 v 50 a 0 all s and d a 300 a 3 d,d b a 1 a 2 +2.4 v +15 v -15 v en v+ v- v o gnd +5 v 35 pf DG406B dg407b


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